787 lines
20 KiB
C++
787 lines
20 KiB
C++
//
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// Created by Palindromic Bread Loaf on 7/21/25.
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//
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#include "cpu.h"
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#include <iostream>
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// CPU Implementation
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void CPU::Reset() {
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A = X = Y = 0;
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SP = 0x01FF;
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PC = 0x8000; // Will be loaded from reset vector
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P = 0x34; // Start in emulation mode
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DB = PB = 0;
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D = 0;
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cycles = 0;
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}
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void CPU::Step() {
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ExecuteInstruction();
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}
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// CPU Helper Methods
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uint8_t CPU::ReadByte(const uint32_t address) {
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cycles++;
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return bus->Read(address);
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}
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uint16_t CPU::ReadWord(const uint32_t address) {
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uint8_t low = ReadByte(address);
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uint8_t high = ReadByte(address + 1);
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return (high << 8) | low;
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}
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void CPU::UpdateNZ8(const uint8_t value) {
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P = (P & ~FLAG_N) | (value & 0x80); // Set N flag if bit 7 is set
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P = (P & ~FLAG_Z) | (value == 0 ? FLAG_Z : 0); // Set Z flag if value is zero
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}
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void CPU::UpdateNZ16(const uint16_t value) {
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P = (P & ~FLAG_N) | ((value & 0x8000) ? FLAG_N : 0); // Set N flag if bit 15 is set
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P = (P & ~FLAG_Z) | (value == 0 ? FLAG_Z : 0); // Set Z flag if value is zero
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}
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// Helper method to write bytes/words to memory
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void CPU::WriteByte(const uint32_t address, const uint8_t value) const {
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bus->Write(address, value);
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}
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void CPU::WriteWord(const uint32_t address, const uint16_t value) const {
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bus->Write(address, value & 0xFF); // Low byte
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bus->Write(address + 1, (value >> 8) & 0xFF); // High byte
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}
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void CPU::ExecuteInstruction() {
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// TODO: Actual Opcode decoding
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switch (const uint8_t opcode = bus->Read(PC++)) {
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case 0xEA: NOP(); break;
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// LDA - Load Accumulator
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case 0xA9: LDA_Immediate(); break; // LDA #$nn or #$nnnn
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case 0xAD: LDA_Absolute(); break; // LDA $nnnn
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case 0xBD: LDA_AbsoluteX(); break; // LDA $nnnn,X
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case 0xB9: LDA_AbsoluteY(); break; // LDA $nnnn,Y
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case 0xA5: LDA_DirectPage(); break; // LDA $nn
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case 0xB5: LDA_DirectPageX(); break; // LDA $nn,X
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case 0xB2: LDA_IndirectDirectPage(); break; // LDA ($nn)
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case 0xB1: LDA_IndirectDirectPageY(); break;// LDA ($nn),Y
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case 0xA1: LDA_DirectPageIndirectX(); break;// LDA ($nn,X)
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case 0xAF: LDA_Long(); break; // LDA $nnnnnn
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case 0xBF: LDA_LongX(); break; // LDA $nnnnnn,X
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// LDX - Load X Register
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case 0xA2: LDX_Immediate(); break; // LDX #$nn or LDX #$nnnn
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case 0xAE: LDX_Absolute(); break; // LDX $nnnn
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case 0xBE: LDX_AbsoluteY(); break; // LDX $nnnn,Y
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case 0xA6: LDX_DirectPage(); break; // LDX $nn
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case 0xB6: LDX_DirectPageY(); break; // LDX $nn,Y
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// LDY - Load Y Register
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case 0xA0: LDY_Immediate(); break; // LDY #$nn or LDY #$nnnn
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case 0xAC: LDY_Absolute(); break; // LDY $nnnn
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case 0xBC: LDY_AbsoluteX(); break; // LDY $nnnn,X
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case 0xA4: LDY_DirectPage(); break; // LDY $nn
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case 0xB4: LDY_DirectPageX(); break; // LDY $nn,X
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//SDA - Store Accumulator
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case 0x8D: STA_Absolute(); break;
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case 0x9D: STA_AbsoluteX(); break;
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case 0x99: STA_AbsoluteY(); break;
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case 0x85: STA_DirectPage(); break;
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case 0x95: STA_DirectPageX(); break;
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case 0x92: STA_IndirectDirectPage(); break;
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case 0x91: STA_IndirectDirectPageY(); break;
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case 0x81: STA_DirectPageIndirectX(); break;
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case 0x8F: STA_Long(); break;
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case 0x9F: STA_LongX(); break;
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//SDX - Store X Register
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case 0x8E: STX_Absolute(); break;
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case 0x86: STX_DirectPage(); break;
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case 0x96: STX_DirectPageY(); break;
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// SDY - Store Y Register
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case 0x8C: STY_Absolute(); break;
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case 0x84: STY_DirectPage(); break;
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case 0x94: STY_DirectPageX(); break;
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default:
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std::cout << "Unknown opcode: 0x" << std::hex << static_cast<int>(opcode) << std::endl;
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break;
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}
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}
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void CPU::NOP() {
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// No operation
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}
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// Load Accumulator Instructions
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void CPU::LDA_Immediate() {
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if (P & FLAG_M) {
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// 8-bit accumulator mode
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const uint8_t value = ReadByte(PC++);
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A = (A & 0xFF00) | value; // Keep high byte, update low byte
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UpdateNZ8(value);
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cycles += 2;
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} else {
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// 16-bit accumulator mode
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A = ReadWord(PC);
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PC += 2;
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UpdateNZ16(A);
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cycles += 3;
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}
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}
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void CPU::LDA_Absolute() {
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const uint16_t address = ReadWord(PC);
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PC += 2;
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if (P & FLAG_M) {
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// 8-bit mode
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const uint8_t value = ReadByte(address);
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A = (A & 0xFF00) | value;
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UpdateNZ8(value);
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cycles += 4;
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} else {
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// 16-bit mode
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A = ReadWord(address);
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UpdateNZ16(A);
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cycles += 5;
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}
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}
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void CPU::LDA_AbsoluteX() {
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const uint16_t base_address = ReadWord(PC);
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PC += 2;
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const uint32_t address = base_address + X;
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// Page boundary crossing adds a cycle in some cases
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if ((base_address & 0xFF00) != (address & 0xFF00)) {
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cycles++;
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}
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if (P & FLAG_M) {
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// 8-bit mode
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const uint8_t value = ReadByte(address);
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A = (A & 0xFF00) | value;
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UpdateNZ8(value);
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cycles += 4;
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} else {
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// 16-bit mode
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A = ReadWord(address);
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UpdateNZ16(A);
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cycles += 5;
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}
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}
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void CPU::LDA_AbsoluteY() {
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uint16_t base_address = ReadWord(PC);
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PC += 2;
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uint32_t address = base_address + Y;
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// Page boundary crossing adds a cycle
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if ((base_address & 0xFF00) != (address & 0xFF00)) {
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cycles++;
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}
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if (P & FLAG_M) {
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// 8-bit mode
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uint8_t value = ReadByte(address);
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A = (A & 0xFF00) | value;
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UpdateNZ8(value);
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cycles += 4;
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} else {
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// 16-bit mode
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A = ReadWord(address);
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UpdateNZ16(A);
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cycles += 5;
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}
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}
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void CPU::LDA_DirectPage() {
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const uint8_t offset = ReadByte(PC++);
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const uint32_t address = D + offset;
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if (P & FLAG_M) {
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// 8-bit mode
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uint8_t value = ReadByte(address);
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A = (A & 0xFF00) | value;
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UpdateNZ8(value);
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cycles += 3;
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} else {
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// 16-bit mode
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A = ReadWord(address);
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UpdateNZ16(A);
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cycles += 4;
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}
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// Extra cycle if D register is not page-aligned
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if (D & 0xFF) cycles++;
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}
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void CPU::LDA_DirectPageX() {
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const uint8_t offset = ReadByte(PC++);
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const uint32_t address = D + offset + (P & FLAG_X ? (X & 0xFF) : X);
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if (P & FLAG_M) {
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// 8-bit mode
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const uint8_t value = ReadByte(address);
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A = (A & 0xFF00) | value;
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UpdateNZ8(value);
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cycles += 4;
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} else {
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// 16-bit mode
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A = ReadWord(address);
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UpdateNZ16(A);
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cycles += 5;
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}
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// Extra cycle if D register is not page-aligned
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if (D & 0xFF) cycles++;
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}
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void CPU::LDA_IndirectDirectPage() {
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const uint8_t offset = ReadByte(PC++);
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const uint32_t pointer_address = D + offset;
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const uint16_t address = ReadWord(pointer_address);
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if (P & FLAG_M) {
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// 8-bit mode
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const uint8_t value = ReadByte(address);
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A = (A & 0xFF00) | value;
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UpdateNZ8(value);
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cycles += 5;
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} else {
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// 16-bit mode
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A = ReadWord(address);
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UpdateNZ16(A);
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cycles += 6;
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}
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// Extra cycle if D register is not page-aligned
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if (D & 0xFF) cycles++;
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}
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void CPU::LDA_IndirectDirectPageY() {
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const uint8_t offset = ReadByte(PC++);
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const uint32_t pointer_address = D + offset;
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const uint16_t base_address = ReadWord(pointer_address);
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const uint32_t address = base_address + Y;
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// Page boundary crossing adds a cycle
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if ((base_address & 0xFF00) != (address & 0xFF00)) {
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cycles++;
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}
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if (P & FLAG_M) {
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// 8-bit mode
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const uint8_t value = ReadByte(address);
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A = (A & 0xFF00) | value;
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UpdateNZ8(value);
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cycles += 5;
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} else {
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// 16-bit mode
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A = ReadWord(address);
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UpdateNZ16(A);
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cycles += 6;
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}
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// Extra cycle if D register is not page-aligned
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if (D & 0xFF) cycles++;
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}
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void CPU::LDA_DirectPageIndirectX() {
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const uint8_t offset = ReadByte(PC++);
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const uint32_t pointer_address = D + offset + (P & FLAG_X ? (X & 0xFF) : X);
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const uint16_t address = ReadWord(pointer_address);
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if (P & FLAG_M) {
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// 8-bit mode
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uint8_t value = ReadByte(address);
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A = (A & 0xFF00) | value;
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UpdateNZ8(value);
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cycles += 6;
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} else {
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// 16-bit mode
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A = ReadWord(address);
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UpdateNZ16(A);
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cycles += 7;
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}
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// Extra cycle if D register is not page-aligned
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if (D & 0xFF) cycles++;
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}
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void CPU::LDA_Long() {
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const uint32_t address = ReadByte(PC++) | (ReadByte(PC++) << 8) | (ReadByte(PC++) << 16);
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if (P & FLAG_M) {
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// 8-bit mode
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const uint8_t value = ReadByte(address);
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A = (A & 0xFF00) | value;
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UpdateNZ8(value);
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cycles += 5;
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} else {
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// 16-bit mode
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A = ReadWord(address);
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UpdateNZ16(A);
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cycles += 6;
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}
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}
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void CPU::LDA_LongX() {
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const uint32_t base_address = ReadByte(PC++) | (ReadByte(PC++) << 8) | (ReadByte(PC++) << 16);
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const uint32_t address = base_address + X;
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if (P & FLAG_M) {
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// 8-bit mode
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const uint8_t value = ReadByte(address);
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A = (A & 0xFF00) | value;
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UpdateNZ8(value);
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cycles += 5;
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} else {
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// 16-bit mode
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A = ReadWord(address);
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UpdateNZ16(A);
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cycles += 6;
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}
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}
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// Load X Register Instructions
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void CPU::LDX_Immediate() {
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if (P & FLAG_X) {
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// 8-bit index mode
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X = ReadByte(PC++);
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UpdateNZ8(X & 0xFF);
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cycles += 2;
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} else {
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// 16-bit index mode
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X = ReadWord(PC);
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PC += 2;
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UpdateNZ16(X);
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cycles += 3;
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}
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}
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void CPU::LDX_Absolute() {
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const uint16_t address = ReadWord(PC);
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PC += 2;
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if (P & FLAG_X) {
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// 8-bit mode
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X = ReadByte(address);
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UpdateNZ8(X & 0xFF);
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cycles += 4;
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} else {
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// 16-bit mode
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X = ReadWord(address);
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UpdateNZ16(X);
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cycles += 5;
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}
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}
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void CPU::LDX_AbsoluteY() {
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const uint16_t base_address = ReadWord(PC);
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PC += 2;
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const uint32_t address = base_address + Y;
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// Page boundary crossing adds a cycle
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if ((base_address & 0xFF00) != (address & 0xFF00)) {
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cycles++;
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}
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if (P & FLAG_X) {
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// 8-bit mode
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X = ReadByte(address);
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UpdateNZ8(X & 0xFF);
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cycles += 4;
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} else {
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// 16-bit mode
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X = ReadWord(address);
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UpdateNZ16(X);
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cycles += 5;
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}
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}
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void CPU::LDX_DirectPage() {
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const uint8_t offset = ReadByte(PC++);
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const uint32_t address = D + offset;
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if (P & FLAG_X) {
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// 8-bit mode
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X = ReadByte(address);
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UpdateNZ8(X & 0xFF);
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cycles += 3;
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} else {
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// 16-bit mode
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X = ReadWord(address);
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UpdateNZ16(X);
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cycles += 4;
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}
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// Extra cycle if D register is not page-aligned
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if (D & 0xFF) cycles++;
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}
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void CPU::LDX_DirectPageY() {
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const uint8_t offset = ReadByte(PC++);
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const uint32_t address = D + offset + (P & FLAG_X ? (Y & 0xFF) : Y);
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if (P & FLAG_X) {
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// 8-bit mode
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X = ReadByte(address);
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UpdateNZ8(X & 0xFF);
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cycles += 4;
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} else {
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// 16-bit mode
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X = ReadWord(address);
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UpdateNZ16(X);
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cycles += 5;
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}
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// Extra cycle if D register is not page-aligned
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if (D & 0xFF) cycles++;
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}
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// Load Y Register Instructions
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void CPU::LDY_Immediate() {
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if (P & FLAG_X) {
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// 8-bit index mode
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Y = ReadByte(PC++);
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UpdateNZ8(Y & 0xFF);
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cycles += 2;
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} else {
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// 16-bit index mode
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Y = ReadWord(PC);
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PC += 2;
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UpdateNZ16(Y);
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cycles += 3;
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}
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}
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void CPU::LDY_Absolute() {
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const uint16_t address = ReadWord(PC);
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PC += 2;
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if (P & FLAG_X) {
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// 8-bit mode
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Y = ReadByte(address);
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UpdateNZ8(Y & 0xFF);
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cycles += 4;
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} else {
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// 16-bit mode
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Y = ReadWord(address);
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UpdateNZ16(Y);
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cycles += 5;
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}
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}
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void CPU::LDY_AbsoluteX() {
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const uint16_t base_address = ReadWord(PC);
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PC += 2;
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const uint32_t address = base_address + X;
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// Page boundary crossing adds a cycle
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if ((base_address & 0xFF00) != (address & 0xFF00)) {
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cycles++;
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}
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if (P & FLAG_X) {
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// 8-bit mode
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Y = ReadByte(address);
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UpdateNZ8(Y & 0xFF);
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cycles += 4;
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} else {
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// 16-bit mode
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Y = ReadWord(address);
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UpdateNZ16(Y);
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cycles += 5;
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}
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}
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void CPU::LDY_DirectPage() {
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const uint8_t offset = ReadByte(PC++);
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const uint32_t address = D + offset;
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if (P & FLAG_X) {
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// 8-bit mode
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Y = ReadByte(address);
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UpdateNZ8(Y & 0xFF);
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cycles += 3;
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} else {
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// 16-bit mode
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Y = ReadWord(address);
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UpdateNZ16(Y);
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cycles += 4;
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}
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// Extra cycle if D register is not page-aligned
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if (D & 0xFF) cycles++;
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}
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void CPU::LDY_DirectPageX() {
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const uint8_t offset = ReadByte(PC++);
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const uint32_t address = D + offset + (P & FLAG_X ? (X & 0xFF) : X);
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if (P & FLAG_X) {
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// 8-bit mode
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Y = ReadByte(address);
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UpdateNZ8(Y & 0xFF);
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cycles += 4;
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} else {
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// 16-bit mode
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Y = ReadWord(address);
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UpdateNZ16(Y);
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cycles += 5;
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}
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// Extra cycle if D register is not page-aligned
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if (D & 0xFF) cycles++;
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}
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//Store operations implementation
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void CPU::STA_Absolute() {
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uint32_t address = ReadWord(PC + 1) | (DB << 16);
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PC += 3;
|
|
|
|
if (P & FLAG_M) { // 8-bit mode
|
|
WriteByte(address, A & 0xFF);
|
|
cycles += 4;
|
|
} else { // 16-bit mode
|
|
WriteWord(address, A);
|
|
cycles += 5;
|
|
}
|
|
}
|
|
|
|
void CPU::STA_AbsoluteX() {
|
|
uint32_t base = ReadWord(PC + 1) | (DB << 16);
|
|
uint32_t address = base + X;
|
|
PC += 3;
|
|
|
|
if (P & FLAG_M) { // 8-bit mode
|
|
WriteByte(address, A & 0xFF);
|
|
cycles += 5;
|
|
} else { // 16-bit mode
|
|
WriteWord(address, A);
|
|
cycles += 6;
|
|
}
|
|
}
|
|
|
|
void CPU::STA_AbsoluteY() {
|
|
uint32_t base = ReadWord(PC + 1) | (DB << 16);
|
|
uint32_t address = base + Y;
|
|
PC += 3;
|
|
|
|
if (P & FLAG_M) { // 8-bit mode
|
|
WriteByte(address, A & 0xFF);
|
|
cycles += 5;
|
|
} else { // 16-bit mode
|
|
WriteWord(address, A);
|
|
cycles += 6;
|
|
}
|
|
}
|
|
|
|
void CPU::STA_DirectPage() {
|
|
uint8_t offset = ReadByte(PC + 1);
|
|
uint32_t address = (D + offset) & 0xFFFF;
|
|
PC += 2;
|
|
|
|
if (P & FLAG_M) { // 8-bit mode
|
|
WriteByte(address, A & 0xFF);
|
|
cycles += 3;
|
|
if (D & 0xFF) cycles++; // Extra cycle if D register low byte != 0
|
|
} else { // 16-bit mode
|
|
WriteWord(address, A);
|
|
cycles += 4;
|
|
if (D & 0xFF) cycles++; // Extra cycle if D register low byte != 0
|
|
}
|
|
}
|
|
|
|
void CPU::STA_DirectPageX() {
|
|
uint8_t offset = ReadByte(PC + 1);
|
|
uint32_t address = (D + offset + X) & 0xFFFF;
|
|
PC += 2;
|
|
|
|
if (P & FLAG_M) { // 8-bit mode
|
|
WriteByte(address, A & 0xFF);
|
|
cycles += 4;
|
|
if (D & 0xFF) cycles++; // Extra cycle if D register low byte != 0
|
|
} else { // 16-bit mode
|
|
WriteWord(address, A);
|
|
cycles += 5;
|
|
if (D & 0xFF) cycles++; // Extra cycle if D register low byte != 0
|
|
}
|
|
}
|
|
|
|
void CPU::STA_IndirectDirectPage() {
|
|
uint8_t offset = ReadByte(PC + 1);
|
|
uint32_t pointer = (D + offset) & 0xFFFF;
|
|
uint32_t address = ReadWord(pointer) | (DB << 16);
|
|
PC += 2;
|
|
|
|
if (P & FLAG_M) { // 8-bit mode
|
|
WriteByte(address, A & 0xFF);
|
|
cycles += 5;
|
|
if (D & 0xFF) cycles++; // Extra cycle if D register low byte != 0
|
|
} else { // 16-bit mode
|
|
WriteWord(address, A);
|
|
cycles += 6;
|
|
if (D & 0xFF) cycles++; // Extra cycle if D register low byte != 0
|
|
}
|
|
}
|
|
|
|
void CPU::STA_IndirectDirectPageY() {
|
|
uint8_t offset = ReadByte(PC + 1);
|
|
uint32_t pointer = (D + offset) & 0xFFFF;
|
|
uint32_t base = ReadWord(pointer) | (DB << 16);
|
|
uint32_t address = base + Y;
|
|
PC += 2;
|
|
|
|
if (P & FLAG_M) { // 8-bit mode
|
|
WriteByte(address, A & 0xFF);
|
|
cycles += 6;
|
|
if (D & 0xFF) cycles++; // Extra cycle if D register low byte != 0
|
|
} else { // 16-bit mode
|
|
WriteWord(address, A);
|
|
cycles += 7;
|
|
if (D & 0xFF) cycles++; // Extra cycle if D register low byte != 0
|
|
}
|
|
}
|
|
|
|
void CPU::STA_DirectPageIndirectX() {
|
|
uint8_t offset = ReadByte(PC + 1);
|
|
uint32_t pointer = (D + offset + X) & 0xFFFF;
|
|
uint32_t address = ReadWord(pointer) | (DB << 16);
|
|
PC += 2;
|
|
|
|
if (P & FLAG_M) { // 8-bit mode
|
|
WriteByte(address, A & 0xFF);
|
|
cycles += 6;
|
|
if (D & 0xFF) cycles++; // Extra cycle if D register low byte != 0
|
|
} else { // 16-bit mode
|
|
WriteWord(address, A);
|
|
cycles += 7;
|
|
if (D & 0xFF) cycles++; // Extra cycle if D register low byte != 0
|
|
}
|
|
}
|
|
|
|
void CPU::STA_Long() {
|
|
uint32_t address = ReadByte(PC + 1) | (ReadByte(PC + 2) << 8) | (ReadByte(PC + 3) << 16);
|
|
PC += 4;
|
|
|
|
if (P & FLAG_M) { // 8-bit mode
|
|
WriteByte(address, A & 0xFF);
|
|
cycles += 5;
|
|
} else { // 16-bit mode
|
|
WriteWord(address, A);
|
|
cycles += 6;
|
|
}
|
|
}
|
|
|
|
void CPU::STA_LongX() {
|
|
uint32_t base = ReadByte(PC + 1) | (ReadByte(PC + 2) << 8) | (ReadByte(PC + 3) << 16);
|
|
uint32_t address = base + X;
|
|
PC += 4;
|
|
|
|
if (P & FLAG_M) { // 8-bit mode
|
|
WriteByte(address, A & 0xFF);
|
|
cycles += 6;
|
|
} else { // 16-bit mode
|
|
WriteWord(address, A);
|
|
cycles += 7;
|
|
}
|
|
}
|
|
|
|
// STX - Store X Register
|
|
void CPU::STX_Absolute() {
|
|
uint32_t address = ReadWord(PC + 1) | (DB << 16);
|
|
PC += 3;
|
|
|
|
if (P & FLAG_X) { // 8-bit mode
|
|
WriteByte(address, X & 0xFF);
|
|
cycles += 4;
|
|
} else { // 16-bit mode
|
|
WriteWord(address, X);
|
|
cycles += 5;
|
|
}
|
|
}
|
|
|
|
void CPU::STX_DirectPage() {
|
|
uint8_t offset = ReadByte(PC + 1);
|
|
uint32_t address = (D + offset) & 0xFFFF;
|
|
PC += 2;
|
|
|
|
if (P & FLAG_X) { // 8-bit mode
|
|
WriteByte(address, X & 0xFF);
|
|
cycles += 3;
|
|
if (D & 0xFF) cycles++; // Extra cycle if D register low byte != 0
|
|
} else { // 16-bit mode
|
|
WriteWord(address, X);
|
|
cycles += 4;
|
|
if (D & 0xFF) cycles++; // Extra cycle if D register low byte != 0
|
|
}
|
|
}
|
|
|
|
void CPU::STX_DirectPageY() {
|
|
uint8_t offset = ReadByte(PC + 1);
|
|
uint32_t address = (D + offset + Y) & 0xFFFF;
|
|
PC += 2;
|
|
|
|
if (P & FLAG_X) { // 8-bit mode
|
|
WriteByte(address, X & 0xFF);
|
|
cycles += 4;
|
|
if (D & 0xFF) cycles++; // Extra cycle if D register low byte != 0
|
|
} else { // 16-bit mode
|
|
WriteWord(address, X);
|
|
cycles += 5;
|
|
if (D & 0xFF) cycles++; // Extra cycle if D register low byte != 0
|
|
}
|
|
}
|
|
|
|
// STY - Store Y Register
|
|
void CPU::STY_Absolute() {
|
|
uint32_t address = ReadWord(PC + 1) | (DB << 16);
|
|
PC += 3;
|
|
|
|
if (P & FLAG_X) { // 8-bit mode
|
|
WriteByte(address, Y & 0xFF);
|
|
cycles += 4;
|
|
} else { // 16-bit mode
|
|
WriteWord(address, Y);
|
|
cycles += 5;
|
|
}
|
|
}
|
|
|
|
void CPU::STY_DirectPage() {
|
|
uint8_t offset = ReadByte(PC + 1);
|
|
uint32_t address = (D + offset) & 0xFFFF;
|
|
PC += 2;
|
|
|
|
if (P & FLAG_X) { // 8-bit mode
|
|
WriteByte(address, Y & 0xFF);
|
|
cycles += 3;
|
|
if (D & 0xFF) cycles++; // Extra cycle if D register low byte != 0
|
|
} else { // 16-bit mode
|
|
WriteWord(address, Y);
|
|
cycles += 4;
|
|
if (D & 0xFF) cycles++; // Extra cycle if D register low byte != 0
|
|
}
|
|
}
|
|
|
|
void CPU::STY_DirectPageX() {
|
|
uint8_t offset = ReadByte(PC + 1);
|
|
uint32_t address = (D + offset + X) & 0xFFFF;
|
|
PC += 2;
|
|
|
|
if (P & FLAG_X) { // 8-bit mode
|
|
WriteByte(address, Y & 0xFF);
|
|
cycles += 4;
|
|
if (D & 0xFF) cycles++; // Extra cycle if D register low byte != 0
|
|
} else { // 16-bit mode
|
|
WriteWord(address, Y);
|
|
cycles += 5;
|
|
if (D & 0xFF) cycles++; // Extra cycle if D register low byte != 0
|
|
}
|
|
} |